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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-27228-2E
ASSP
For Power Supply Applications (General Purpose DC/DC Converter)
2-Channel DC/DC Converter IC
with Overcurrent Protection Symmetrical-Phase Type
MB3886
s DESCRIPTION
The MB3886 is a symmetrical-phase type of two-channel, DC/DC converter IC using pulse width modulation (PWM) , incorporating an overcurrent protection circuit (requiring no current sense resistor) and an overvoltage protection circuit. Providing high output driving capabilities, the MB3886 is suitable for down-conversion. The MB3886 adopts both synchronous rectification to provide high efficiency and symmetrical phasing (two antiphase triangular waves) which contributes to making the input capacitor small. The MB3886 contains a 5-volt regulator resulting in a reduced number of components used. It also contains a variety of protection features which output the protection status upon detection of an overvoltage or overcurrent while reducing the number of external protective devices required. The result is an ideal built-in power supply for driving products with high speed CPU's such as home TV game devices and notebook PC's. This product is covered by US Patent Number 6,147,477.
s FEATURES
* * * * Overcurrent protection circuit (requiring no current sense resistor) and overvoltage protection circuit Power-supply voltage range : 5.5 V to 18 V Synchronous rectification system providing high efficiency PSIG pins (open-drain) to output the protection status (Continued)
s PACKAGE
30-pin plastic SSOP
(FPT-30P-M02)
MB3886
(Continued) * Symmetrical-phase system reducing the input capacitor loss * Built-in channel control function * Reference voltage : 3.5 V 1% * Error amplifier threshold voltage : 1.25 V 1% (0 C to 85 C) * Oscillator frequency range : 10 kHz to 500 kHz * Built-in circuit for load-independent soft-start and discharge control * Totem-pole type output for N-ch MOSFET
s PIN ASSIGNMENT
(TOP VIEW)
PSIG1 : 1 CTL1 : 2 ILIM1 : 3 CT : 4 RT : 5 SGND : 6 CS1 : 7 -INE1 : 8 FB1 : 9 +INC1 : 10 OUT1-1 : 11 VS1 : 12 CB1 : 13 OUT2-1 : 14 PGND : 15
30 : PSIG2 29 : CTL2 28 : ILIM2 27 : VREF 26 : VCC 25 : CSCP 24 : CS2 23 : -INE2 22 : FB2 21 : +INC2 20 : OUT1-2 19 : VS2 18 : CB2 17 : OUT2-2 16 : VB
(FPT-30P-M02)
2
MB3886
s PIN DESCRIPTION
Pin No. Pin name I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PSIG1 CTL1 ILIM1 CT RT SGND CS1 -INE1 FB1 +INC1 OUT1-1 VS1 CB1 OUT2-1 PGND VB OUT2-2 CB2 VS2 OUT1-2 +INC2 FB2 -INE2 CS2 CSCP VCC VREF ILIM2 CTL2 PSIG2 O I I Description CH1 protection status output terminal CH1 control terminal "H" level : CH1 ON state "L" level : CH1 OFF state and protection status reset CH1 overcurrent detection resistor connection terminal
Triangular waveform oscillation frequency setting capacitor connection terminal Triangular waveform oscillation frequency setting resistor connection terminal Ground terminal CH1 soft-start capacitor connection terminal I O I O CH1 error amp. inverting input terminal CH1 error amp. output terminal CH1 overvoltage comparator noninverting input terminal CH1 totem-pole output terminal (External main-side FET gate drive) CH1 boot capacitor connection terminal Connect a capacitor between the CB1 and VS1 terminals. CH1 totem-pole output terminal (External synchronous-rectification-side FET gate drive) Output circuit bias output terminal CH2 totem-pole output terminal (External synchronous-rectification-side FET gate drive) CH2 boot capacitor connection terminal Connect a capacitor between the CB2 and VS2 terminals. CH2 totem-pole output terminal (External main-side FET gate drive) CH2 error amp. output terminal CH2 error amp. inverting input terminal
CH1 external main-side FET source connection terminal O
Ground terminal O O
CH2 external main-side FET source connection terminal O O I CH2 overvoltage comparator noninverting input terminal
CH2 soft-start capacitor connection terminal Timer-latch short-circuit protection capacitor connection terminal Reference voltage, control circuit power supply terminal O I I O Reference voltage output terminal CH2 overcurrent detection resistor connection terminal CH2 control terminal "H" level : CH2 ON state "L" level : CH2 OFF state and protection status reset CH2 protection status output terminal 3
MB3886
s BLOCK DIAGRAM
VCC 26 5 V Reg. FB1 9 -INE1 8 CS1 7 VREF 10 A +INC1 10 CTL1 2
1.47 V CTL1 3.8 k
16 VB
10 A
< CH1 > Error Amp.1 - + + 1.25 V OVP Comp.1 + -
Latch1-1
13 CB1 PWM Comp.1 + -
Drive1-1
11 OUT1-1 12 VS1
R SQ
Dead Time Modulation1
Latch2-1
Drive2-1
14 OUT2-1
CTL1 R QS
Current Protection Logic
PSIG1 1
- + 3 ILIM1
FB2 22
10 A
< CH2 > Error Amp.2 - + + 18 CB2 PWM Comp.2 + -
Drive1-2
-INE2 23 CS2 24 VREF 10 A +INC2 21 CTL2 29
3.8 k
1.25 V OVP Comp.2 + -
Latch1-2
20 OUT1-2 19 VS2
1.47 V CTL2 R
Dead Time Modulation2
Latch2-2
Drive2-2
17 OUT2-2 15 PGND
SQ PSIG2 30
CTL2
Current Protection Logic
R QS
- + 28 ILIM2
SCP Comp. 10 A
2.1 V - - + 1.3 V 2.1 V 2.3 V CTL1 and CTL2 CT1 CT2 bias 1.3 V VCC
CSCP 25 S R Latch Latch3 UVLO
OSC 4 CT 5 RT
Ref (3.5 V) Power 27 6 VREF SGND
4
MB3886
s ABSOLUTE MAXIMUM RATINGS
Parameter Power-supply voltage Boot voltage Output current Peak output current Power dissipation Storage temperature Symbol VCC VCB IO IOP PD Tstg Conditions CB terminal
Rating Min -55 Max 20 25 120 800 770* +125
Unit V V mA mA mW C
Duty 5% (t = 1 / fOSC x Duty) Ta +25 C
* : The packages are mounted on the dual-sided epoxy board (10 cm x 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5
MB3886
s RECOMMENDED OPERATING CONDITIONS
Parameter Power-supply voltage Boot voltage Reference voltage output current Bias output current Input voltage Output voltage Output current Peak output current Oscillator frequency Timing resistor Timing capacitor Boot capacitor Reference voltage output capacitor Bias output capacitor Soft-start capacitor Short-circuit detection capacitor Overcurrent detection setting resistor Operating ambient temperature Symbol VCC VCB IOR IOB VIN VINC VCTL VPSIG IO IOP fOSC RT CT CB CREF CVB CS CSCP RLIM Ta Conditions CB terminal VREF terminal VB terminal -INE terminal +INC terminal CTL terminal PSIG terminal Duty 5% (t = 1 / fosc x Duty) VREF terminal VB terminal Value Min 5.5 -1 -1 0 0 0 0 -100 -700 10 6.8 150 1.0 0.1 -30 Typ 12 290 9.1 330 0.1 0.1 4.7 0.1 0.01 1 +25 Max 18 23 0 0 VCC - 1.8 VCC VREF 15 100 700 500 12 15000 1.0 1.0 10 1 1 10 +85 Unit V V mA mA V V V V mA mA kHz k pF F F F F F k C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
6
MB3886
s ELECTRICAL CHARACTERISTICS
Symbol VREF 1. Reference Voltage Block [Ref] Output voltage VREF/ VREF Input stability Load stability Short-circuit output current 2. Bias Voltage Output voltage Block [VB] 3. Triangular Waveform Oscillator Block [OSC] Oscillator frequency Frequency/ temperature variation Line Load Ios VB fOSC fOSC/ fOSC VTH VH VRST VTH ICSCP ILIM VIO VTH IB Pin No. 27 27 27 27 27 16 4 (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 C) Values Unit Conditions Min Typ Max Ta = +25 C Ta = 0 C to +85 C VCC = 5.5 V to 18 V VREF = 0 mA to -1 mA VREF = 2 V RT = 9.1 k, CT = 330 pF Ta = 0 C to 85 C VCC = 3.465 -28 5.0 260 4.7 1.7 0.63 -14 106 1.44 -200 0.8 3.500 0.5* 1 3 -14 5.1 290 3.535 10 10 -7 5.2 320 5.1 2.5 0.73 -6 130 1.50 2 V % mV mV mA V kHz % V V V V A A mV V nA
Parameter
4
1*
Threshold 4. Undervoltvoltage age (VCC) Hysteresis Lockout Circuit width Block [UVLO] Reset voltage 5. Short-circuit Protection Circuit Block [SCP] 6. Overcurrent Protection Circuit Block [OCP] 7. Overvoltage Protection Circuit Block [OVP] 8. Latches Block [Latch1 to Latch3] 9. Protection Status Output Circuit Block [PSIG] Threshold voltage Input source current ILIM terminal input current Offset voltage Threshold voltage Input bias current Reset voltage Output leakage current Output lowlevel voltage
26 26 26 25 25
4.9 0.35* 2.1 0.68 -10 118 1* 1.47 -30 1.4 0.1
3, 28 RT = 9.1 k 3, 28 10, 21 +INC = 10, 21 +INC = 0 V 2, 29 CTL = 1, 30 PSIG = 5 V 1, 30 PSIG = 1 mA
VRST
V A V
ILEAK VOL
40 0.4
* : Typical design value
(Continued)
7
MB3886
(VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 C) Values Unit Conditions Min Typ Max FB = 1.7 V, Ta = +25 C FB = 1.7 V, Ta = 0 C to 85 C -14 1.241 1.2375 -200 60 2.4 1.5 1.2 -10 1.2500 1.2500 -20 100 1500* 2.7 0.8 -100 9.0 1.3 2.02 -6 1.259 1.2625 1.0 -45 2.2 A V V nA dB kHz V V A mA V V
Parameter 10. Soft-start Circuit Block [CS]
Symbol ICS
Pin No. 7, 24
Charge current
Threshold voltage Input bias current 11. Error Amp. Block [Error Amp.] Voltage gain Frequency bandwidth Output voltage Output source current Output sink current 12. PWM Comparator Block [PWM Comp.] 13. Dead Time Control Block [DTC] Threshold voltage
VTH1 VTH2 IB AV BW VFBH VFBL ISOURCE ISINK VTL VTH
8, 23 8, 23
8, 23 -INE = 0 V 9, 22 DC 9, 22 AV = 0 dB 9, 22 9, 22 9, 22 FB = 1.7 V 9, 22 FB = 1.7 V 9, 22 Duty cycle = 0% 9, 22 Duty cycle = Dtr
Maximum duty cycle
Dtr
11, 20 RT = 9.1 k, CT = 330 pF Duty 5% (t = 1 / fOSC x Duty) Duty 5% (t = 1 / fOSC x Duty) OUT1 = -100 mA, CB = 13.5 V, VS = 12 V OUT1 = 100 mA, CB = 13.5 V, VS = 12 V Duty 5% (t = 1 / fOSC x Duty) Duty 5% (t = 1 / fOSC x Duty)
73
78 -700* 900*
83
% mA mA V V mA mA V V
Output current (main side)
ISOURCE1 11, 20 ISINK1 VOH1 VOL1 11, 20 11, 20 11, 20
Output voltage (main side) 14. Output Block [Drive]
VCB - 2.5 VCB - 0.9 2.5
VS + 0.9 VS + 1.4 -750* 900* 4.1 1.0 1.4
Output current ISOURCE2 14, 17 (synchronous rectification ISINK2 14, 17 side) Output voltage (synchronous rectification side) VOH2 VOL2
14, 17 OUT2 = -100 mA 14, 17 OUT2 = 100 mA
* : Typical design value
(Continued)
8
MB3886
(Continued)
Parameter 14. Output Block [Drive] Diode voltage Dead time Output ON condition Output OFF condition Input current 16. General Power-supply current Symbol VD tD VON VOFF ICTL ICC Pin No. (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 C) Values Unit Conditions Min Typ Max 30 2 0 -14 0.9 100 -10 15 1.1 170 VREF 0.8 -6 23 V ns V V A mA
13, 18 VB = 10 mA 11, 14 OUT1 = OUT2 = OPEN, 20, 17 VS = 0 V 2, 29 Output ON state 2, 29 Output OFF state 2, 29 26
15. Channel control Block [CTL]
9
MB3886
s TYPICAL CHARACTERISTICS
Supply Current vs. Supply Voltage
18 16 14 12 10 8 6 4 2 0 0 5 10 15 20 Ta = +25 C
Reference Voltage vs. Supply Voltage Reference voltage VREF (V)
5 4 3 2 1 0 0 Ta = +25 C VREF = 0 mA
20
Supply current ICC (mA)
5
10
15
20
Supply voltage VCC (V) Reference Voltage vs. Ambient Temperature Reference voltage VREF (%)
2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -40 -20 0 20 40 60 80 100 VCC = 12 V VREF = 0 mA
Supply voltage VCC (V)
Ambient temperature Ta ( C)
Triangular waveform oscillation frequency fOSC (kHz)
1000
Ta = +25 C VCC = 12 V RT = 9.1 k
Triangular waveform oscillation frequency fOSC (kHz)
Triangular Waveform Oscillation Frequency vs. Timing Capacitor
Triangular Waveform Oscillation Frequency vs. Timing Resistor
CT = 150 pF CT = 330 pF 100
1000
100
10
10 CT = 15000 pF Ta = +25 C VCC = 12 V 100
1 10
100
1000
10000
100000
1 1
10
Timing capacitor CT (pF)
Timing resistor RT (k)
(Continued)
10
MB3886
(Continued) Triangular Waveform Oscillation Frequency vs. Supply Voltage
Triangular waveform oscillation frequency fOSC (kHz)
320 315 310 305 300 295 290 285 280 275 270 265 260 0 Ta = +25 C RT = 9.1 k CT = 330 pF
Triangular waveform oscillation frequency fOSC/fOSC (%)
Triangular Waveform Oscillation Frequency vs. Ambient Temperature
2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -40 -20 0 20 40 60 80 100 VCC = 12 V RT = 9.1 k CT = 330 pF
5
10
15
20
Supply voltage VCC (V) Error Amp. Gain/Phase vs. Frequency (CH1)
40 30 Av Ta = +25 C 180
Ambient Temperature Ta ( C)
VCC = 12 V
Phase (deg)
Gain AV (dB)
20 10 0 -10 -20 -30 -40 100 1k 10 k
90
240 k 4.7 k IN 2.4 k (23) 8 10 F 7 (24) 4.7 k
+
0
-90 -180 100 k 1M 10 M
- + +
9 (22) OUT
Error Amp.1 (Error Amp.2)
Frequency f (Hz) Error Amp. Threshold Voltage vs. Ambient Temperature (CH1)
1.264 1.262 1.26 1.258 1.256 1.254 1.252 1.25 1.248 1.246 1.244 1.242 1.24 1.238 1.236 -40
Power Dissipation vs. Ambient Temperature
800 770 700 600 500 400 300 200 100 0 -40 -20 0 20 40 60 80 100
Error amplifier threshold voltage VTH (V)
-20
0
20
40
60
80
100
Ambient Temperature Ta ( C)
Power dissipation PD (mW)
VCC = 12 V
Ambient Temperature Ta ( C) 11
MB3886
s FUNCTIONAL DESCRIPTION
1. DC/DC Converter Functions
(1) Reference voltage Block The reference voltage circuit generates a temperature-compensated reference voltage (typically 3.5 V) using the voltage supplied from the power supply terminal (pin 26) . The voltage is used as the reference voltage for the IC's internal circuitry. The reference voltage can be used to supply a load current of up to 1 mA to an external device through the VREF terminal (pin 27) . (2) Triangular waveform oscillator Block The triangular waveform oscillator incorporates a timing capacitor and a timing resistor connected respectively to the CT terminal (pin 4) and RT terminal (pin 5) to generate oscillating triangular waveforms CT1 (amplitude of 1.3 V to 2.1 V) and CT2 (amplitude of 1.3 V to 2.1 V in antiphase with CT1) . The symmetrical-phase system using the two opposite-phase triangular waves reduces the input ripple current, resulting in a smaller input capacitor. The oscillating triangular waveforms are input to the IC's internal PWM comparator and can be output to an external device through the CT terminal. (3) Error Amp. Block (Error Amp.) The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. It supports a wide range of in-phase input voltages from 0 V to "Vcc - 1.8 V", allowing easy setting from the external power supply. In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverting input terminal of the error amplifier, enabling stable phase compensation to be provided for the system. (4) PWM comparator Block (PWM Comp.) The PWM comparator is a voltage-pulse width modulator that controls the output duty depending on the input voltage. Main side : Turns the output transistor on in the intervals in which the error amplifier output voltage is higher than the triangular wave voltage. Synchronous rectification sides : Turns the output transistor on in the intervals in which the error amplifier output voltage is lower than the triangular wave valtage. (5) Output Block The output circuits on the main side and on the synchronous rectification side are both in the totem pole configuration, capable of driving an external N-ch MOS FET. In addition, because the output drive ability (700 mA Max : Duty 5%) is high, the gate - source capacity is large and the FET of low ON resistor can be used.
12
MB3886
2. Channel Control Function
Channels are turned on and off depending on the voltage levels at the CTL1 terminal (pin 2) and CTL2 terminal (pin 29). Channel On/Off Setting Conditions CTL terminal voltage level Channel output state CTL1 L H L H CTL2 L L H H CH1 OFF ON OFF ON CH2 OFF OFF ON ON
3. Protective Functions
(1) Timer-Latch Short-Circuit Protection Circuit Block The short-circuit detection comparator (SCP Comp.) provided for the two channels detects the output voltage level and, if either channel output voltage falls below the short-circuit detection voltage, the timer circuit is actuated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 25) . When the capacitor voltage reaches about 0.68 V, the circuit turns off the output transistor and sets the dead time to 100%. Once the protection circuit is actuated, it can be reset by turning the power supply off and on again. (See "SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT".) (2) Undervoltage Lockout Circuit Block The transient state or a momentary drops in supply voltage, which occurs when the power supply is turned on, may cause the control IC to malfunction, resulting in breakdown or degradation of the system. To prevent such malfunctions, the undervoltage lockout circuit detects the internal reference voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the CSCP terminal (pin 25) at the "L" level. System operation is restored when the supply voltage reaches the threshold voltage of the undervoltage lockout circuit. (3) Overcurrent Protection Circuit The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the main-side FET's drain and source by the mainside FET ON resistor and sets the latch to fix the main and synchronous rectification outputs of the relevant channel at the "L" level. The detection current value can be set by resistor RLIM1 connected between the mainside FET's drain and the ILIM1 terminal (pin 3) and resistor RLIM2 connected between the drain and the ILIM2 pin (pin 28) . (See "SETTING THE OVERCURRENT DETECTION CURRENT".) (4) Overvoltage Protection Circuit (OVP) When the overvoltage detection comparator (OVP Comp.) provided for each channel detects the output voltage level exceeding its threshold voltage, the overvoltage protection circuit sets the latch to fix only the main output of the relevant channel at the "L" level and the synchronous-rectification output at the "H" level. (See "SETTING THE OVERVOLTAGE DETECTION VOLTAGE".)
13
MB3886
s SETTING THE OUTPUT VOLTAGE
(FB2) 22 VO FB1 9 VO = R1 (-INE2) 23 -INE1 R2 (CS2) 24 CS1 7 1.25 V 8 - + + Error Amp. 1.25 V R2 (R1 + R2)
CH1, 2
s SETTING THE OSCILLATION FREQUENCY
The oscillation frequency can be set by connecting the timing capacitor (CT) to the CT terminal (pin 4) and timing resistor (RT) to the RT terminal (pin 5) . Oscillation frequency : fOSC 870000 fOSC (kHz) = CT (pF) *RT (k) :
14
MB3886
s SETTING THE SOFT-START AND DISCHARGE TIMES
To prevent surge currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 and CS2) to the CS1 terminal (pin 7) for channel 1 and the CS2 terminal (pin 24) for channel 2, respectively. Setting the each control terminals (CTL1 and CTL2) from "L" to "OPEN" switches SW1 and SW2 from B to A to charge the external soft-start capacitors (CS1 and CS2) connected to the CS1 and CS2 terminals at 10 A. The error amplifier output (FB1 or FB2) is determined by comparison between the lower one of the potentials at two noninverting input terminals (1.25 V CS terminal voltages) and the inverting input terminal voltage (-INE) . The FB terminal voltage during the soft-start period is therefore determined by comparison between the -INE terminal and CS terminal voltages. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor connected to the CS terminal is charged. The soft-start time is obtained from the following equation : Soft-start time : ts (time to output 100%) ts (s) = 0.125 x CS (F) : Setting the each control terminals (CTL1 and CTL2) from "OPEN" to "L" switches SW1 and SW2 from A to B. Then the IC discharges the soft-start capacitors (CS1 and CS2) charged at about 3.4 V using the internally set discharge resistor (Rs = 3.8 k) and lowers the output voltage with a time constant of about 1/10 of the soft: start time regardless of the DC/DC converter load current. The discharge time is obtained from the following equation : Discharge time : toff (time to output 10%) toff (s) = 0.0126 x CS (F) :
= 3.4 V
CS terminal voltage
= 1.25 V
Error Amp. Voltage compared to -INE voltage
= 0.125 V =0V
Soft-start time ts
Discharge time toff
OPEN CTL signal L
15
MB3886
VREF
10 F
(FB2) 22 FB1 9 (-INE2) 23 -INE1 8 (CS2) 24 CS1 Cs1 (Cs2) 7 VREF 10 F SW1 (SW2) (CTL2) 29 CTL1 2 A B Rs = 3.8 k - + + 1.25 V Error Amp.
< Soft-start circuit >
s TREATMENT OF UNUSED CS PINS
When the soft-start function is not used, the CS1 terminal (pin 7) and CS2 terminal (pin 22) should be left open.
"Open" 7 CS1 CS2 24
"Open"
< Operation Without Soft-Start Setting > 16
MB3886
s SETTING THE OVERCURRENT DETECTION CURRENT
The overcurrent protection circuit is actuated upon completion of the soft-start period. If an overcurrent flows, the circuit detects the increase in the voltage between the main-side FET's drain and source by the main-side FET ON resistor (RON) and sets the latch to fix the main and synchronous rectification outputs of the relevant channel at the "L" level. At the same time, the circuit fixes the PSIG1 terminal (pin 1) at the "L" level when the overcurrent is detected on CH1 or the PSIG2 terminal (pin 30) at the "L" level when it is detected on CH2. The detection current value can be set by the resistors (RLIM1 and RLIM2) connected between the main-side FET's drain and the ILIM1 terminal (pin 3) /ILIM2 terminal (pin 28) , respectively. Note that the overcurrent protection circuit works for each channel separately. Detection current value : IOCP IOCP (A) = : ILIM (A) x RLIM () Ron () (Vin (V) - Vo (V) ) x Vo (V) - 2 x Vin (V) x fOSC (Hz) x L (H)
RON : Main-side FET ON resistor, Vin : Input voltage, Vo : DC/DC converter output voltage fOSC : Oscillation frequency, L : Coil inductance
s TREATMENT OF UNUSED ILIM PINS
When the overcurrent protection circuit is not used, the ILIM1 terminal (pin 3) and ILIM2 terminal (pin 28) should be shorted to the SGND terminal (pin 6) using the shortest possible connection.
3 ILIM1
ILIM2 28
6 SGND
< Operation Without Using the ILIM Terminals >
17
MB3886
s TREATMENT OF UNUSED PSIG PINS
When the PSIG terminals are not used, the PSIG1 terminal (pin 1) and PSIG2 terminal (pin 30) should be shorted or open to the SGND terminal (pin 6) .
"Open" 1 PSIG1 PSIG2 30 1 PSIG1 PSIG2 30
"Open"
6 SGND
< Operation Without Using the PSIG Terminals >
18
MB3886
s SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT
Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier's output level to the reference voltage. While the DC/DC converter load conditions are stable on both channels, the short-circuit detection comparator keeps its output at the "H" level and the CSCP terminal (pin 25) remains at the input standby voltage (VSTB = 50 : mV) . If a load condition changes rapidly due to a short circuit of the load, causing the output voltage to drop, the shortcircuit detection comparator changes its output to the "L" level. This causes the external short-circuit protection capacitor Cscp connected to the CSCP terminal to be charged at 10 A. Short-circuit detection time : tscp tscp (s) = 0.068 x Cscp (F) : When the capacitor Cscp is charged to the threshold voltage (VTH = 0.68 V) , the protection circuit sets the latch : and turns off the external FET (setting the dead time to 100%) . At this time, the latch input is closed and the CSCP terminal is held at the input latch voltage (VI = 50 mV) . The protection circuit shuts off both channels : even when a short circuit is detected on only either.
s PROCESSING WITHOUT USING THE CSCP TERMINAL
When the timer-latch short-circuit protection circuit is not used, the CSCP terminal (pin 25) should be shorted to SGND using the shortest possible connection.
6 SGND
CSCP 25
< Operation Without Using the CSCP Terminal >
19
MB3886
s SETTING THE OVERVOLTAGE DETECTION VOLTAGE
An overvoltage output from the DC/DC converter can be detected by connecting external resistors from the DC/ DC converter output voltage to the +INC1 terminal (pin 10) and +INC2 terminal (pin 21) of the overvoltage comparators (OVP Comp. 1 and 2) . When the DC/DC converter output voltage rises and the detection voltage exceeds the setting voltage, the output of the overvoltage comparator (OVP Comp. 1, 2) becomes the "H" level and the latch is set to fix only the main output of the relevant channel at the "L" level and the synchronous-rectification output at the "H" level. At the same time, the overvoltage protection circuit fixes the PSIG1 terminal (pin 1) at the "L" level when the overvoltage is detected on CH1 or the PSIG2 terminal (pin 30) at the "L" level when it is detected on CH2. Note that the overvoltage protection circuit works for each channel separately. Overvoltage detection voltage : VOVP VOVP (V) = 1.47 x (R3 () + R4 () ) / R4 () : To reset the actuated protection circuit, either set the CTL1 terminal (pin 2) or CTL2 terminal (pin 29) to the "L" level, or decrease the VCC voltage to the reset voltage (1.7 V Min) or less.
VO CTL1 (CTL2) R3
(+INC2) 21 10 +INC1
+ -
OVP Comp.
R S
Q
R4
1.47 V
20
MB3886
s OUTPUT STATES DURING PROTECTION CIRCUIT OPERATION
The table below lists the output states with individual protection circuits actuated. Output terminal CH1 Protection circuit Overcurrent protection circuit Overvoltage protection circuit Short-circuit protection circuit CH1 CH2 CH1 CH2 CH1 CH2 OUT1-1 L Active L Active L L OUT2-1 L Active H Active L L PSIG1 L H L H H H OUT1-2 Active L Active L L L CH2 OUT2-2 Active L Active H L L PSIG2 H L H L H H
s RESETTING THE LATCH OF EACH PROTECTION CIRCUIT
When each protection circuit (overvoltage, overcurrent, or short-circuit protection circuit) detects an abnormal state or event, it sets the latch to fix the output at the "L" level. The PSIG1 terminal (pin 1) or PSIG2 terminal (pin 30) is fixed at the "L" level when the overvoltage or overcurrent protection circuit detects an overvoltage or overcurrent. When a protection circuit operates, the latch can be released by reentering the power supply or setting the CTL1 terminal (pin 2) or CTL2 terminal (pin 29) to the "L" level. The overvoltage and overcurrent protection circuits work for each channel separately. Use the CTL1 and CTL2 terminals to unlatch CH1 and CH2, respectively. The short-circuit protection circuit fixes the outputs of both channels upon detection of a short circuit even on either. Set both of the CTL1 and CTL2 terminals to the "L" level to unlatch the two channels. Unlatching Conditions Operation circuit Overcurrent protection circuit Overvoltage protection circuit CTL1 OPEN L OPEN L OPEN Short-circuit protection circuit L OPEN L : Unlatched, x : Not unlatched CTL2 OPEN OPEN L L OPEN OPEN L L x x x x Channels unlatched CH1 x CH2 x x
21
MB3886
s NOTE ON IC'S INTERNAL POWER CONSUMPTION
The oscillation frequency of an IC and the total gate charge of FETs largely affects the internal dissipation of the IC. Pay attention to the following point with respect to the internal power consumption of the IC when applications are used. IB (mean current) is obtained from the following equation, assuming Qg1 and Qg2 as the total gate charges applied to the gate capacitors (Ciss1, Ciss2, Crss1, Crss2) of external FETs Q1 and Q2. Current per channel IB (A) = I1 + I2 = Ibias1 x : t1 t + Qg1 t2 t + Ibias2 x t + Qg2 t (Ibias1 = Ibias2 = 3 mA) :
As the current consumption by the IC, excluding IB, is about 15 mA, the power consumption is obtained from the following equation : Power consumption : Pc Pc (W) = 0.015 x VCC (V) + 2 x VCC (V) *IB (A) - VB (V) *IB (A)
22
MB3886
Vin
VCC 26 5V
IB 16
VB CVB CB1 Q1 Crss1 OUT1-1 Ciss1 VS1 Ciss Crss2 Q2 A L1 VO1
13 I1
Drive 1-1
11 12
I2
Drive 2-1
14 15
OUT2-1 PGND
2
t VOUT1-1
VOUT2-1
I1 t1 I2 t2
Bias current Ibias1 3 mA
Bias current Ibias2 3 mA
t
See "Power Consumption vs. Input Voltage" on the next page as a reference and use the above method of obtaining the power consumption to design your application of the IC taking account of the "Power Dissipation vs. Ambient Temperature" characteristic in the "TYPICAL CHARACTERISTICS" section.
23
MB3886
Power Consumption vs. Input Voltage (Qg Parameters)
1.2 1.1 1.0
Power consumption PC (W)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5 6 7 8 9 10 11 12 13 14 15 16 Ta = +25 C fOSC = 290 kHz SW1 = OFF SW2 = OFF 17 18 19 20 Qg1 = Qg2 = 70 nC Qg1 = Qg2 = 50 nC Qg1 = Qg2 = 30 nC Qg1 = Qg2 = 20 nC Qg1 = Qg2 = 10 nC
Input voltage Vin (V)
Power Consumption vs. Input Voltage (fosc Parameter)
1.2 1.1
Power consumption PC (W)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5 6 7 8 9 10 11 12 13 14 15 Ta = +25 C Qg1 = Qg2 = 20 nC SW1 = OFF SW2 = OFF 16 17 18 19 20 fOSC = 500 kHz fOSC = 300 kHz fOSC = 200 kHz fOSC = 100 kHz fOSC = 10 kHz
Input voltage Vin (V)
24
Vin 26 5 V Reg.
C9 4.7 F C3 0.1 F C1 OUT1-1 Drive1-1 Q2 C18 1 F 82 F x3 + C4 12 H C5 0.1 F L1
VCC
C17 0.1 F
C2 82 F
VB 16 D1 13
(3.3 V/2 A)
FB1 9
10 A
< CH1 >
CB1
A CS1
C11 0.1 F 1.25 V OVP Comp.1 OUT2-1 Drive2-1 VREF 10 A 3.8 k
C10 0.022 F R9 R10 12 k -INE1
Error Amp.1 PWM Comp.1 + - VS1 12 14 11 - + +
A
VO1
9.1 k
s SAMPLE CIRCUIT
R12 5.6 k
8 7
R11
+INC1 10 2
1.47 V Latch 1-1 R CTL1 SQ
9.1 k R13 5.6 k
CTL1
SW1
+ -
Daed Time Modulation1 Latch CTL1 2-1 R Current
QS R1 1 k Protection Logic
Protection control signal FB2 22
10 A
1 PSIG1 ILIM1 3
- +
< CH2 >
D3
B CS2
VREF Drive1-2 10 A 3.8 k 1.25 V OVP Comp.2 C13 0.1 F +INC2
C12 0.022 F R14 R15 13 k -INE2
CB2 18
C6 0.1 F Q3 Q4 C19 1 F L2 15 H + C7 82 F x2
B
VO2
(5 V/2 A)
10 k
23 24
Error Amp.2 - + + PWM Comp.2 + -
R17 3.3 k
C8 0.1 F
R16
OUT1-2 20 VS2 19 OUT2-2 17 PGND 15
10 k Latch 1-2 1.47 R V CTL2 SQ Daed Time Modulation2 Latch CTL2
R18 3.3 k
21 CTL2 29 SW2
2-2
+ -
Drive2-2
PSIG2 30
QS
R Current Protection Logic
- +
ILIM2 28
R5 820
Protection control signal SCP Comp. 10 A 2.3 V CTL1 and CTL2 UVLO CSCP 25
C14 0.01 F
- - +
2.1 V 1.3 V 2.1 V 1.3 V CT1 CT2 bias VCC SR Latch Latch3 OSC
(3.5 V)
Ref Power 27
C15 330 pF R19 9.1 k
6
VREF SGND
C16 0.1 F
MB3886
4 5 CT RT
25
MB3886
s PARTS LIST
COMPONENT Q1, Q3 Q2, Q4 D1, D3 L1 L2 C2 C3, C5, C6, C8 C4 C7 C9 C10 C11, C13, C16 C12 C14 C15 C17 C18, C19 R1 R5 R9 R10, R11 R12, R13 R14 R15, R16 R17, R18 R19 ITEM FET FETKYTM Diode Coil Coil OS-CONTM Ceramics Condenser OS-CONTM OS-CONTM Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor SPECIFICATION VDS = 30 V, Qg = 17 nC (Max) VDS = 30 V, Qg = 14 nC (Max) VF = 0.3 V (Max) , IF = 1 A 12 H 15 H 82 F 0.1 F 82 F x 3 82 F x 2 4.7 F 0.022 F 0.1 F 0.022 F 0.01 F 330 pF 0.1 F 1 F 1 k 820 12 k 9.1 k 5.6 k 13 k 10 k 3.3 k 9.1 k 3.5 A, 21 m 2.8 A, 25.9 m 16 V 16 V 6.3 V 6.3 V 10 V 25 V 16 V 25 V 50 V 50 V 25 V 16 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/8 W 1/16 W 1/16 W VENDOR IR IR ROHM SUMIDA TDK SANYO KYOCERA SANYO SANYO MURATA MURATA KYOCERA MURATA MURATA MURATA MURATA MURATA KOA KOA KOA KOA KOA KOA KYOCERA KOA KOA PARTS No. IRF7807 IRF7807D1 RB495D CDRH125-120 SLF12555T150M2R8 16SVP82M CM21W5R104K16 6SVP82M 6SVP82M GRM42-6B475K10 GRM39B473K25 CM21W5R104K16 GRM39B223K25 GRM39B103K50 GRM39R331K50 GRM39F104Z25 GRM40B105K16 RK73G1J102D RK73G1J821D RK73G1J123D RK73G1J912D RK73G1J562D RK73G1J223D CR21-103F RK73G1J332D RK73G1J912D
Note : IR : International Rectifier Corp. ROHM : ROHM CO., LTD. SUMIDA : Sumida Electric Co., Ltd. TDK : TDK Corporation SANYO : SANYO Electric Co., Ltd. KYOCERA : Kyocera Corporation MURATA : Murata Manufacturing Co., Ltd. KOA : KOA Corporation FETKY is a trademark of International Rectifier Corp. OS-CON is a trademark of SANYO Electric Co., Ltd.
26
MB3886
s REFERENCE DATA
Conversion Efficiency vs. Load Current (CH1)
100 Ta = +25 C 3.3 V output SW1 = OFF SW2 = ON
90
Conversion efficiency (%)
80
70
60
50 Vin = 8.5 V Vin = 10 V Vin = 12 V 100 m 1 10
40
30 10 m
Load current IL (A)
Conversion Efficiency vs. Load Current (CH2)
100 Ta = +25 C 5 V output SW1 = ON SW2 = OFF
90
Conversion efficiency (%)
80
70
60
50 Vin = 8.5 V Vin = 10 V Vin = 12 V 100 m 1 10
40
30 10 m
Load current IL (A)
27
MB3886
s NOTES ON USE
* Take account of common impedance when designing the earth line on a printed wiring board. * Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools, and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 k to 1 M resistors in series. * Do not apply a negative voltage. - Applying a negative voltage of -0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction.
s ORDERING INFORMATION
Model name MB3886PFV Package 30-pin plastic SSOP (FPT-30P-M02) Remarks
28
MB3886
s PACKAGE DIMENSION
30-pin plastic SSOP (FPT-30P-M02)
* 9.700.10(.382.004)
* : This dimension does not include resin protrusion.
+0.20
1.25 -0.10
+.008 (Mounting height) .049 -.004 0.10(.004)
INDEX
5.600.10 (.220.004)
7.600.20 (.299.008)
6.60(.260) NOM
0.650.12(.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
9.10(.358)REF 0 10 0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F30003S-2C-3
Dimensions in mm (inches)
29
MB3886
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0209 (c) FUJITSU LIMITED Printed in Japan

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